Low-Cost Phasor Measurement Unit

Overview

A Phasor Measurement Unit (PMU) is a device that takes precise, time-stamped electrical measurements of a power grid — capturing voltage, frequency, and phase angle — synchronised to a common time reference. That synchronisation is what makes PMUs powerful: it lets grid operators compare measurements taken at different locations at the exact same instant, giving a real-time picture of what's happening across the whole network.

Commercial PMUs are expensive and bulky, limiting how widely they can be deployed. This final year project repurposed existing power measurement hardware and built a fully functional, low-cost PMU firmware in Rust on a Raspberry Pi — targeting real grid monitoring accuracy and full compliance with the IEEE C37.118 synchrophasor standard.

Hardware Platform

The firmware runs on a custom board providing:

• RC voltage divider networks — step the three-phase grid voltage (±325V) safely down to ±0.5V for the ADC
• MCP3914 ADC — an 8-channel, 24-bit delta-sigma converter, synchronously sampling all channels over a 20MHz SPI interface at ~9,875 Hz
• u-blox MAX-M10S GNSS module — provides UTC time accurate to 60 nanoseconds from the satellite network, connected over I2C

Pipeline Architecture

The firmware is structured as a four-stage pipeline, each running in its own thread and passing data forward via channels:

Data Acquisition → Data Processing → Data Storage → Data Transmission

This separation keeps each concern isolated and makes the system easy to test — both the ADC and time provider are defined as Rust traits, meaning fake hardware implementations can be swapped in for unit and integration tests without needing physical devices.

Time Synchronisation

Measurements are only meaningful with precise timestamps. The GNSS module delivers an accurate UTC second, but measurements happen thousands of times per second — sub-second resolution is essential.

The solution was the Raspberry Pi's GPU timer — a free-running 64-bit counter driven by a 1MHz clock, independent of the CPU and OS scheduler. Accessing it requires memory-mapping the hardware System Timer register directly from /dev/mem, giving 1 microsecond resolution with zero OS overhead. Anchoring this counter to the GNSS second pulse produces a precise full UTC timestamp for every single ADC sample.

The GNSS parser runs on a dedicated background thread, continuously reading NMEA messages over I2C and updating a shared, mutex-protected timestamp — keeping the acquisition loop free to focus entirely on sampling speed.

Signal Processing

Once samples arrive from acquisition, the processing stage computes:

• Synchrophasor — the magnitude and phase angle of each voltage waveform, calculated via FFT using the rustfft crate
• Frequency — derived from the FFT output
• ROCOF — Rate of Change of Frequency, used for detecting grid instability events
• RMS voltage — effective magnitude per phase

Before the FFT, each signal passes through a 2531-coefficient FIR filter to remove noise and out-of-band interference. Spline interpolation enforces a consistent effective sampling rate and corrects for any timing gaps. A ring buffer (BoundedVecDeque) keeps the most recent samples in memory for continuous windowed analysis. Parallel processing via rayon keeps throughput high across all channels.

IEEE C37.118 Compliance

PMU output is transmitted using the IEEE C37.118.2 protocol — the international standard for synchrophasor data transfer — over TCP/IP. The implementation covers:

• Data frames, configuration frames (CFG-2), header frames, and command frames
• Binary encoding with CRC-CCITT validation on every frame
• Multi-client support with connection and command frame handling

A separate WebSocket server streams live measurements to a web dashboard for real-time waveform and phasor visualisation.

Storage

All measurements are persisted to a local SQLite database in JSON format, supporting over two days of continuous storage. Historical data can be queried, exported as CSV or JSON, or replayed with timing accuracy for post-hoc analysis.

Results

The system met the majority of its requirements: processing latency under 100 microseconds, microsecond-level timestamps, and a complete pipeline from raw ADC samples to IEEE C37.118-formatted output. The trait-based design proved its value during development — the fake ADC and fake time provider let the processing and transmission stages be tested fully on a laptop before any hardware was involved.

Formal phasor accuracy verification against a reference-grade PMU was not possible within the project scope, leaving that validation as future work.